As disclosed in, for example, JP-A-10-264765, JP-A-10-297420, and JP-A-2005-88748, an electrical load drive circuit has been proposed that drives an electrical load, (e.g., airbag squib) by using a high-side transistor and a low-side transistor. FIG. 14 shows a conventional airbag squib drive circuit for driving an airbag squib 110 (e.g., resistor). The squib drive circuit is implemented on an integrated circuit (IC) chip 100 and the squib 110 is connected to the IC chip 100. The IC chip 100 includes a high-side metal-oxide semiconductor field-effect transistor (MOSFET) Q10 and a low-side MOSFET Q11.
In the IC chip 100, a current detection resistor 101 detects a load current flowing through the squib 110. A comparator 102 compares a voltage drop across the current detection resistor 101 with a reference voltage. An output of the comparator 102 is fed to a high-side gate driver 103. A control signal Sc of a control logic 105 is fed to the high-side gate driver 103 via an AND gate 104. An output of the high-side gate driver 103 is fed to the gate of the high-side MOSFET Q10 so that the high-side gate driver 103 can drive the high-side MOSFET Q10.
A control signal Sc of a control logic 107 is fed to a low-side gate driver 109 via an NAND gate 108. An output of the low-side gate driver 109 is fed to the gate of the low-side MOSFET Q11 so that the low-side gate driver 109 can drive the low-side MOSFET Q11. A timer signal St of a timer 106 is fed to each of the AND gate 104 and the NAND gate 108.
As shown in FIG. 15, during a time period (i.e., between times t1, t3) when both the control signal Sc and the timer signal St are set to a high level, a gate-source voltage Vds11 of the low-side MOSFET Q11 is held high so that the low-side MOSFET Q11 is fully turned on. In contrast, during the time period, a gate source voltage Vgs10 of the high-side MOSFET Q10 is adjusted so that the load current flowing through the squib 110 can be held constant.
As shown in FIG. 15, during the time period when both the control signal Sc and the timer signal St are set to the high level, a drain-source voltage Vds11 of the low-side MOSFET 11 is low, because the low-side MOSFET Q11 is fully turned on. Accordingly, heat generated by the low-side transistor Q11 is small, and temperature of the low-side transistor Q11 is low. Therefore, the low-side transistor Q11 has a sufficient thermal margin so that the low-side transistor Q10 can be prevent from being thermally damaged or destroyed.
In contrast, during the time period, a drain-source voltage Vds10 of the high-side MOSFET Q10 is high, because a large portion of a power supply voltage Vdd is applied between the drain and source of the high-side MOSFET Q10. Accordingly, heat generated by the high-side MOSFET Q10 is large, and temperature of the high-side MOSFET Q10 becomes high. Therefore, the high-side transistor Q10 does not have the sufficient thermal margin so that the high-side transistor Q10 may be thermally damaged or destroyed.
Further, the large heat generated by the high-side transistor Q10 may affect peripheral circuits of the IC chip 100 and active elements placed near the high-side transistor Q10. One approach to this problem is to increase the size of the high-side MOSFET Q10. However, the increase in size results in an increase in cost.